Hardware engineers can now auto-generate test assertions that actually work — 96% functional accuracy

A system called ChatSVA uses AI to automatically write SystemVerilog Assertions, the test code that catches bugs in chip designs. It went from barely functional to 96% correct, meaning engineers can now skip the tedious, error-prone manual writing and let the AI do it.

Functional verification — the process of checking that a chip design actually works — eats up more than half of the development timeline and budget for every new processor or ASIC. Manual assertion writing is where most of that time gets lost. If this holds up in production, it collapses a major bottleneck in chip design cycles. The catch: this is a research paper with a public demo, not a deployed tool inside a major design house yet.