AI learns to write hardware verification rules — cutting functional errors by 70%

Researchers built a system that learns how to translate English descriptions into formal verification code (SystemVerilog Assertions), a tedious task that hardware engineers currently do by hand. The system outperforms existing AI approaches by 31% on functional correctness, which means fewer bugs slip through hardware design verification.

Hardware verification is a bottleneck in chip design. Engineers spend weeks translating specification documents into precise mathematical assertions that catch bugs before manufacturing. This system learns patterns from examples and applies them to new specifications, reducing the manual work. If the approach scales beyond research settings, it could compress a weeks-long process into hours — but the system still fails on about 30% of real-world cases, so hardware teams aren't replacing engineers yet.